Efficient layout extraction to fight malicious manipulation of complex integrated circuits

Integrated Flow for Reverse Engineering of Nanoscale Technologies is the topic of a talk to be given by Infineon Technologies together with Raith at next year’s Asia and South Pacific Design Automation Conference (ASP-DAC) in Tokyo, Japan. 

schematic of reverse engineering workflow
Reverse engineering workflow

Together with Infineon Technologies, Fraunhofer EMFT, and the TU Munich, we have been working on a solution for quantitative evaluation of the success of a complete reverse engineering process by comparing the error between the generated layout and the original design as a figure of merit (FOM). A circuit graph of an ECC encryption and circuit block partitioning will later be extracted from the layout. Raith’s main role concerns fast and accurate acquisition of raw image data.

graph showing final stitching error after reverse engineering
final stitching error

The need to establish an effective and efficient process of reverse engineering is becoming increasingly urgent in view of the potential risks of piracy and malicious manipulation of complex integrated circuits built into technologies of 45 nm and less.

ASP-DAC is designed to cultivate and promote interactions and presentations of novel ideas among EDA researchers/developers and system/circuit/device level designers. It therefore provides the perfect platform for introducing a new tool for acquisition and synthesis of large-area images and layout extraction. Meet us there and listen to our talk on January 22, 2019 at 1:30 pm. To check out the whole program, visit http://tsys.jp/aspdac/2019/program/program.html

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